1. Related Invention
The present invention is related to "Digital Waveform Analyzer", filed Jan. 11, 1988, Serial No. 07/142,652, now U.S. Pat. No. 4,873,647.
2. Field of the Invention
The present invention relates in general to a method and apparatus for partitioning Boolean equations representative of logical relationships between input and output digital signals for implementation into actual physical logic devices. More particularly, the present invention relates to a method and apparatus for performing partitioning of Boolean logic equations based upon user generated cost values, physical constraints, and pin directives into actual physical devices wherein a plurality of possible partitioning solutions are tabulated in order of cost value.
3. Statement of the Problem
In the design of digital systems, a problem exists with the incompatibility of the various components available from different manufacturers. For example, the manufacturer of a computer will specify the various input and output binary signals necessary to communicate with its computer. Likewise, the manufacturers of the peripheral devices that interconnect with the computer also provide detailed signal specifications for interconnecting the inputs and the outputs of the devices. While some manufacturers of peripheral devices specifically manufacture the device to communicate with a given processor, it is more common to design an interface circuit that allows a peripheral device to communicate with a computer or another interface device. These interface devices provide the necessary logic and timing capability. Some peripheral devices have several interface circuits for each different function they perform. This problem with compatibility is not limited to computers and digital devices but is a common problem between any digital device that must communicate with another digital device. In addition, a need exists for a system which automatically aids in the design of state machines, decoders, and the like.
The above related invention provides an automatic approach to determine the necessary Boolean logic equations for the design of such interface circuits so that a peripheral device or system is fully compatible with the computer.
A need exists, therefore, to take the Boolean logic design equations, whether manually or automatically generated, and to partition the equations into a set of physical logic devices.
Currently there exists hundreds of logic devices of different types available to a designer for implementation in digital structures. These commercially available devices include programmable devices such as programmable logic devices (PLDs), programmable logic arrays (PLAs), programmable logic elements (PLEs), programmable logic sequencers (PLS), and programmable memories (PROMs); standard logic such as 7400 series TTL, 4000 series CMOS, and 10K series ECL; standard cells; and gate arrays. It becomes confusing and difficult for logic designers to process the shear magnitude (i.e., several thousand) of commercially available devices while still paying attention to such details as propagation delays, costs, family type, etc.
Significant engineering time can be consumed to manually partition Boolean logic design equations into commercially available devices. Furthermore, manual partitioning does not guarantee that the optimum design (i.e., the lowest cost, etc.) has been achieved.
A further need exists for an automatic system wherein the user of the system can specify physical constraints such as propagation delay, logic family, etc. and wherein the user can further specify partitioning directives such as signals appearing on specific pin assignments.
4. Solution to the Problem
The present invention provides a solution to the above problem by providing an automated partitioning system for designing, on a computer, the physical implementation of Boolean logic design equations into a set of physical logic devices that meets a user's constraints, partitioning directives and design goals.
The use of such constraints, partitioning directives, and design goals enables the user to significantly reduce the time spent in evaluating architectures and devices from different manufacturers.
Furthermore, the present invention, as opposed to prior manual layout approaches, automatically generates an optimal layout of inputs and outputs on one or more devices, again, thereby significantly reducing engineering time in the overall design effort.
The present invention further solves the above problem by ordering the possible partitioning solutions according to a cost value. The present invention provides output solutions in minutes compared to manual approaches that may take weeks of engineering effort.